A complex programmable logic device (CPLD) of a fault-tolerant computer system is located between a service system and a baseboard management controller (BMC) system, and is mainly used for extending peripheral functions of a master chip of the BMC system, thereby acting as a bridge between the BMC system and the service system. The CPLD in the system is responsible for critical tasks such as power-up and power-down time sequence control of the service system, acquisition of various state parameters of the CPU, and peripheral bus simulation.
Due to reasons such as the improvement of functions and system maintenance, a demand for upgrading logics inside the CPLD exists. FIG. 1 shows an existing solution for performing online upgrade on the CPLD through an ordinary In System Program (ISP). As shown in FIG. 1, in this solution, at a hardware level, four general purpose input/output (GPIO) interfaces of an embedded CPU are respectively connected to TDI, TDO, TCK and TMS signal pins of a joint test action group (JTAG) module on the CPLD; while at a software level, an ISP service software is run on the embedded CPU, for parsing an upgrade file. On the foregoing software and hardware basis, the online upgrade of logics inside the CPLD is implemented through a single upgrade file.
Online load of upgrade software can be achieved by adopting this solution; however, in a procedure of performing an upgrade operation on the CPLD, the upgrade operation cannot be interrupted, and once the upgrade operation is started, the existing logics of the CPLD become invalid. Therefore, the service system is inevitably forced to power down first, and then the upgrade operation is completed till the upgrade ends. In this way, the system downtime is increased, and the system availability is lowered.